Microprocessor Programming Card: http://www.bamafolks.com/~randy/students/embedded/Z80_intro.html ---------------------------------------------------------------- |Mnemonic |SZHPNC|Description |Notes | |----------+------+---------------------+----------------------| |adc a,s |***V0*|Add with Carry |A=A+s+CY | |adc hl,ss |**?V0*|Add with Carry |HL=HL+ss+CY | |add a,s |***V0*|Add |A=A+s | |add hl,ss |--?-0*|Add |HL=HL+ss | |add ix,pp |--?-0*|Add |IX=IX+pp | |add iy,rr |--?-0*|Add |IY=IY+rr | |and s |***P00|Logical AND |A=A&s | |bit b,m |?*1?0-|Test Bit |m&{2^b} | |call cc,nn|------|Conditional Call |If cc call | |call nn |------|Unconditional Call |-(SP)=PC,PC=nn | |ccf |--?-0*|Complement Carry Flag|CY=~CY | |CP s |***V1*|Compare |A-s | |cpd |****1-|Compare and Decrement|A-(HL),HL=HL-1,BC=BC-1| |cpdr |****1-|Compare, Dec., Repeat|cpd till A=(HL)or BC=0| |cpi |****1-|Compare and Increment|A-(HL),HL=HL+1,BC=BC-1| |cpir |****1-|Compare, Inc., Repeat|cpi till A=(HL)or BC=0| |cpl |--1-1-|Complement |A=~A | |daa |***P-*|Decimal Adjust Acc. |A=BCD format | |dec s |***V1-|Decrement |s=s-1 | |dec xx |------|Decrement |xx=xx-1 | |dec ss |------|Decrement |ss=ss-1 | |di |------|Disable Interrupts | | |djnz e |------|Dec., Jump Non-Zero |B=B-1 till B=0 | |ei |------|Enable Interrupts | | |ex (sp),hl|------|Exchange |(SP)<->HL | |ex (sp),xx|------|Exchange |(SP)<->xx | |ex af,af' |------|Exchange |AF<->AF' | |ex de,hl |------|Exchange |DE<->HL | |exx |------|Exchange |qq<->qq' (except AF)| |halt |------|Halt | | |im n |------|Interrupt Mode | (n=0,1,2)| |in a,(n) |------|Input |A=(n) | |in r,(c) |***P0-|Input |r=(C) | |inc r |***V0-|Increment |r=r+1 | |inc (hl) |***V0-|Increment |(HL)=(HL)+1 | |inc xx |------|Increment |xx=xx+1 | |inc (xx+d)|***V0-|Increment |(xx+d)=(xx+d)+1 | |inc ss |------|Increment |ss=ss+1 | |ind |?*??1-|Input and Decrement |(HL)=(C),HL=HL-1,B=B-1| |indr |?1??1-|Input, Dec., Repeat |ind till B=0 | |ini |?*??1-|Input and Increment |(HL)=(C),HL=HL+1,B=B-1| |inir |?1??1-|Input, Inc., Repeat |ini till B=0 | |jp (hl) |------|Unconditional Jump |PC=(HL) | |jp (xx) |------|Unconditional Jump |PC=(xx) | |jp nn |------|Unconditional Jump |PC=nn | |jp cc,nn |------|Conditional Jump |If cc jp | |jr e |------|Unconditional Jump |PC=PC+e | |jr cc,e |------|Conditional Jump |If cc jr(cc=C,NC,NZ,Z)| |ld dst,src|------|Load |dst=src | |ld a,i |**0*0-|Load |A=i (i=I,R)| |ldd |--0*0-|Load and Decrement |(DE)=(HL),HL=HL-1,# | |lddr |--000-|Load, Dec., Repeat |ldd till BC=0 | |ldi |--0*0-|Load and Increment |(DE)=(HL),HL=HL+1,# | |ldir |--000-|Load, Inc., Repeat |ldi till BC=0 | |neg |***V1*|Negate |A=-A | |nop |------|No Operation | | |or s |***P00|Logical inclusive OR |A=Avs | |otdr |?1??1-|Output, Dec., Repeat |OUtd till B=0 | |otir |?1??1-|Output, Inc., Repeat |OUTI till B=0 | |out (c),r |------|Output |(C)=r | |out (n),a |------|Output |(n)=A | |outd |?*??1-|Output and Decrement |(C)=(HL),HL=HL-1,B=B-1| |outi |?*??1-|Output and Increment |(C)=(HL),HL=HL+1,B=B-1| |pop xx |------|Pop |xx=(SP)+ | |pop qq |------|Pop |qq=(SP)+ | |push xx |------|Push |-(SP)=xx | |push qq |------|Push |-(SP)=qq | |res b,m |------|Reset bit |m=m&{~2^b} | |ret |------|Return |PC=(SP)+ | |ret cc |------|Conditional Return |If cc ret | |reti |------|Return from Interrupt|PC=(SP)+ | |retn |------|Return from NMI |PC=(SP)+ | |rl m |**0P0*|Rotate Left |m={CY,m}<- | |rla |--0-0*|Rotate Left Acc. |A={CY,A}<- | |rlc m |**0P0*|Rotate Left Circular |m=m<- | |rlca |--0-0*|Rotate Left Circular |A=A<- | ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemonic |SZHPNC|Description |Notes | |----------+------+---------------------+----------------------| |rld |**0P0-|Rotate Left 4 bits |{A,(HL)}={A,(HL)}<- ##| |rr m |**0P0*|Rotate Right |m=->{CY,m} | |rra |--0-0*|Rotate Right Acc. |A=->{CY,A} | |rrc m |**0P0*|Rotate Right Circular|m=->m | |rrca |--0-0*|Rotate Right Circular|A=->A | |rrd |**0P0-|Rotate Right 4 bits |{A,(HL)}=->{A,(HL)} ##| |rst p |------|Restart | (p=0H,8H,10H,...,38H)| |sbc a,s |***V1*|Subtract with Carry |A=A-s-CY | |sbc hl,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY | |scf |--0-01|Set Carry Flag |CY=1 | |set b,m |------|Set bit |m=mv{2^b} | |sla m |**0P0*|Shift Left Arithmetic|m=m*2 | |sra m |**0P0*|Shift Right Arith. |m=m/2 | |srl m |**0P0*|Shift Right Logical |m=->{0,m,CY} | |sub s |***V1*|Subtract |A=A-s | |xor s |***P00|Logical Exclusive OR |A=Axs | |----------+------+--------------------------------------------| | F |-*01? |Flag unaffected/affected/reset/set/unknown | | S |S |Sign flag (Bit 7) | | Z | Z |Zero flag (Bit 6) | | HC | H |Half Carry flag (Bit 4) | | P/V | P |Parity/Overflow flag (Bit 2, V=overflow) | | N | N |Add/Subtract flag (Bit 1) | | CY | C|Carry flag (Bit 0) | |-----------------+--------------------------------------------| | n |Immediate addressing | | nn |Immediate extended addressing | | e |Relative addressing (PC=PC+2+offset) | | (nn) |Extended addressing | | (xx+d) |Indexed addressing | | r |Register addressing | | (rr) |Register indirect addressing | | |Implied addressing | | b |Bit addressing | | p |Modified page zero addressing (see RST) | |-----------------+--------------------------------------------| |DEFB n(,...) |Define Byte(s) | |DEFB 'str'(,...) |Define Byte ASCII string(s) | |DEFS nn |Define Storage Block | |DEFW nn(,...) |Define Word(s) | |-----------------+--------------------------------------------| | A B C D E |Registers (8-bit) | | AF BC DE HL |Register pairs (16-bit) | | F |Flag register (8-bit) | | I |Interrupt page address register (8-bit) | | IX IY |Index registers (16-bit) | | PC |Program Counter register (16-bit) | | R |Memory Refresh register | | SP |Stack Pointer register (16-bit) | |-----------------+--------------------------------------------| | b |One bit (0 to 7) | | cc |Condition (C,M,NC,NZ,P,PE,PO,Z) | | d |One-byte expression (-128 to +127) | | dst |Destination s, ss, (BC), (DE), (HL), (nn) | | e |One-byte expression (-126 to +129) | | m |Any register r, (HL) or (xx+d) | | n |One-byte expression (0 to 255) | | nn |Two-byte expression (0 to 65535) | | pp |Register pair BC, DE, IX or SP | | qq |Register pair AF, BC, DE or HL | | qq' |Alternative register pair AF, BC, DE or HL | | r |Register A, B, C, D, E, H or L | | rr |Register pair BC, DE, IY or SP | | s |Any register r, value n, (HL) or (xx+d) | | src |Source s, ss, (BC), (DE), (HL), nn, (nn) | | ss |Register pair BC, DE, HL or SP | | xx |Index register IX or IY | |-----------------+--------------------------------------------| | + - * / ^ |Add/subtract/multiply/divide/exponent | | & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR | | <- -> |Rotate left/right | | ( ) |Indirect addressing | | ( )+ -( ) |Indirect addressing auto-increment/decrement| | { } |Combination of operands | | # |Also BC=BC-1,DE=DE-1 | | ## |Only lower 4 bits of accumulator A used | ---------------------------------------------------------------- Figure 1: Programming Card for Zilog Z80 microprocessor